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ATmega128
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During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the interrupt flag. The output compare pin is changed on the timer clock and is not
synchronized to the processor clock.
Timer/Counter
Interrupt Mask
Bit
7
6
5
4
3
2
1
0
Register – TIMSK
Read/ W rite
Initial Value
OCIE2
R/ W
0
TOIE2
R/ W
0
TICIE1
R/ W
0
OCIE1A
R/ W
0
OCIE1B
R/ W
0
TOIE1
R/ W
0
OCIE0
R/ W
0
TOIE0
R/ W
0
TIMSK
? Bit 1 – OCIE0: Timer/Counter0 Output Compare Match Interrupt Enable
W hen the OCIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match interrupt is enabled. The corresponding interrupt is executed if
a compare match in Timer/Counter0 occurs, i.e., when the OCF0 bit is set in the Timer/Counter
Interrupt Flag Register – TIFR.
? Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
W hen the TOIE0 bit is written to one, and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter Interrupt
Flag Register – TIFR.
Timer/Counter
Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
– TIFR
Read/ W rite
Initial Value
OCF2
R/ W
0
TOV2
R/ W
0
ICF1
R/ W
0
OCF1A
R/ W
0
OCF1B
R/ W
0
TOV1
R/ W
0
OCF0
R/ W
0
TOV0
R/ W
0
TIFR
? Bit 1 – OCF0: Output Compare Flag 0
The OCF0 bit is set (one) when a compare match occurs between the Timer/Counter0 and the
data in OCR0 – Output Compare Register0. OCF0 is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, OCF0 is cleared by writing a logic one to
the flag. W hen the I-bit in SREG, OCIE0 (Timer/Counter0 Compare Match Interrupt Enable), and
OCF0 are set (one), the Timer/Counter0 Compare Match Interrupt is executed.
? Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hard-
ware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared
by writing a logic one to the flag. W hen the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Inter-
rupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow Interrupt is executed. In
P W M mode, this bit is set when Timer/Counter0 changes counting direction at $00.
108
2467X–AVR–06/11
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